Development of a fpga based average digital filter
This paper presents the modeling, design and probe of a FPGA-based digital average filter. PLD-based hardware implementation is recommended due to average filters use simple computational operations. The filter was used into a discrete time control system in order to reduce AWGN.
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| Formato: | Artículo (Article) |
| Lenguaje: | Español (Spanish) |
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Universidad Distrital Francisco José de Caldas
1999
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| Acceso en línea: | http://hdl.handle.net/11349/19520 |